Cache Simulator with LRU Replacement and Multi-Level Cache Design
Overview
Overview
I created a C++ adjustable cache simulator to improve my comprehension of computer architecture and memory systems. By calculating cache hits and misses and supporting various cache sizes, associativity levels, and block sizes, the program simulates how a CPU cache reacts to memory accesses.
A second-level cache, adjustable block sizes, and automatic categorization of mandatory, conflict, and capacity cache misses were eventually added to the simulator's LRU (Least Recently Used) replacement strategy. This project gave participants hands-on experience with memory hierarchy, cache organization, and performance optimization principles that are frequently applied in contemporary processors. The entire project was constructed in C++ with modular functions and dynamic data structures.
Tools and Components Used
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C++
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Cache Memory Simulation
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Computer Architecture
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LRU (Least Recently Used) Algorithm
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Multi-Level Cache Design
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Dynamic Memory (STL Vectors)
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File Input and Output
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Command-Line Programming
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Performance Analysis
Key Steps
2. Created Dynamic Cache Sets
Instead of hard-coding cache sizes, I dynamically created cache sets using nested vectors. This allows the simulator to support different associativity values and numbers of cache entries.
1. Designed the Cache Structure
The foundation of the simulator was a custom cache line structure that stores the information needed for every cache entry. Each line keeps track of whether it contains valid data, its tag, and the last time it was accessed for the LRU replacement policy.
3. Implemented Cache Lookup
Each memory address is converted into a block number, set index, and tag before searching the cache for a matching entry.
4. Detected Cache Hits
Whenever the requested tag already exists inside the correct cache set, the simulator records a hit and updates the access timestamp.
5. Implemented the LRU Replacement Algorithm
When a cache set becomes full, the least recently used cache line is replaced with the new block.
6. Added an L2 Cache
To better simulate modern processors, I added a second-level cache. If data is found in L2, it is copied back into L1 instead of accessing main memory.
7. Classified Cache Misses
Using a fully associative cache, the simulator identifies why each miss occurred.
8. Flexible Command-Line Configuration
The simulator accepts user input from the command line, allowing many cache configurations without changing the code.
9. Generated Output
